The present invention relates in general to integrated circuits and in particular to storage devices whose structure comprises a dielectric layer of capacitive coupling having ferroelectric features and/or a high dielectric constant, both in the case that the storage device employs the features of residual polarization of the ferroelectric oxide or the capacitive coupling through the dielectric oxide for storing information in the form of electric charge.
Ferroelectric and particularly dielectric compounds based on mixed oxides or equivalent compounds with ferroelectric features are materials used in different fields and particularly in the manufacture of integrated structures on a semiconductor or dielectric substrate. Piezoelectric filters, ultrasonic transducers which employ the piezoelectric features, infrared transducers, optical sensors employing features of pyroelectricity, optical modulation devices, and optical diaphragms based on the employment of electro-optical features are some applications of these materials.
The possibility of manufacturing extremely thin dielectric films of materials having ferroelectric features has favored the development of nonvolatile storage devices with ferroelectric capacitors, which employ the stability in time of the residual polarization of the thin layer of ferroelectric material of the capacitor. These devices (storage cells) have been developed by virtue of their potential to be manufactured in extremely compact size, so as to increase the storage capacity and the level of integration of the whole integrated device or their marked ability to preserve the information even in particularly hard conditions.
Ferroelectric dielectrics which are commonly used in the manufacturing processes of integrated devices are lead zirconate titanates, PbZr(1-x)Ti(x)O3, commonly known with the acronym PZT, bismuth and strontium tantalate or Sr2Bi2Ta2O9, commonly known with the acronym SBT or YI, and the lanthanum and bismuth titanates, commonly known with the acronym BLT. These are among the most used materials for manufacturing the so-called FeRAM storage devices.
Another similar dielectric material (also with ferroelectric features) used as a dielectric layer, in particular as dielectric interpoly of capacitive coupling between a control gate structure (wordline) and the floating gate of the cell in DRAM cell structures, is barium and strontium titanate, Ba(x)Sr(1-x)TiO3, also known with the acronym BST.
The materials preferably used for exploiting the ferroelectric features thereof in FeRAM are the above mentioned PZT and also the SBT or the BLT, whereas the BST is most frequently used in the DRAMs by virtue of an increased possibility of depositing extremely thin films thereof, having a high dielectric constant, free from defects.
The techniques of deposition of the layers of dielectric compounds with ferroelectric features can be various, such as by xe2x80x9csputteringxe2x80x9d, or by chemical deposition from the vapor phase (CVD) wherein a decomposable compound, commonly an organometallic compound of precursor metals, is deposited from the vapor phase on a suitable substrate.
Another method of formation of these layers is the so-called xe2x80x9csol-gelxe2x80x9d method, wherein a solution of precursor compounds is used in order to form a film on substrate, commonly by thermal decomposition of several applications of sol-gel. There is also a method based on the creation of a xe2x80x9cmistxe2x80x9d of ionized drops of a solution of a metallo-organic precursor compound, which are deposited on the wafers. Once the solvent is evaporated, the metallo-organic compound is decomposed at high temperature in a strongly oxidizing environment, so as to form a film of composite oxide. This technique is known in the literature as xe2x80x9cLiquid Source Misted Chemical Depositionxe2x80x9d or briefly LSMCD. Other methods of preparation are known in the literature.
Leaving out of consideration the particular function of the thin-film capacitor of dielectric material with high dielectric constant, optionally also with marked ferroelectric features, and the relevant integrated structure to which it belongs, whether that of a FeRAM, of a DRAM or other, the formation of the thin-film capacitor in the course of a manufacturing process of a common semiconductor integrated device, for example in CMOS technology, entails a number of problems due to a precise risk of exposure of the thin layer, generally based on oxides, to hydrogen. As a matter of fact, in the common course of a manufacturing process of integrated devices, there are a number of operations where hydrogen is present that remains partly trapped or incorporated in the wafer during the manufacture, typically in the semiconductor silicon substrate.
For example in a CMOS process, the devices (transistors) defined in the active areas can be exposed to an annealing treatment in hydrogen atmosphere for neutralizing bonds which are left xe2x80x9cdanglingxe2x80x9d in the semiconductor, in order to reduce problems of superficial charge at the interface between the semiconductor and the gate oxide. During this annealing treatment, hydrogen can remain trapped in the substrate, which thus becomes a source of hydrogen diffusion during the working life of the integrated device. Other sources of exposure to hydrogen can be identified in the so-called xe2x80x9cback-endxe2x80x9d steps of the process, during the formation of metallizing aluminum layers, the steps of formation of tungsten plugs for the contacts and formation of the IDL layers, wherein the process conditions are such that the presence of hydrogen is implicated.
Hydrogen can also be present during the sealing and encapsulating steps of the integrated device, in the case of ceramic xe2x80x9cpackaging.xe2x80x9d Also, during the working life of the devices, a certain diffusion of hydrogen inside the device can take place.
The effects of degradation of a dielectric film, optionally with ferroelectric features, generally formed of an oxide or more frequently of mixed oxides or equivalent compounds, upon exposure to hydrogen are well-known and discussed in the literature. In particular, a hydrogen degradation of the ferroelectric film of an FeRAM causes a contraction of the hysteresis curve, thus reducing the separation between the logical values 1 and 0 on the ordinate axis, which effect can bring about a difficulty in the discrimination criteria in the reading step of the information stored in the ferroelectric film capacitor. In the case of a DRAM, the degradation of the thin dielectric film of interpoly capacitive coupling determines a loss of electric charge stored in the floating gate through the wordline.
The suggestions made until now in order to overcome this critical aspect of the dielectric and ferroelectric materials having a high dielectric constant against a hardly avoidable hydrogen exposure have been several.
European published patent application EP-A-0 605 980 discloses a growth PECVD technique of a Si3N4 and SiON layer having a low hydrogen content, as an inter-dielectric state of an FeRAM device, using TEOS (Si(OC2H5)4) and N2, instead of the common mixture of SiH4/NH3/N2.
U.S. Pat. No. 5,523,595 discloses the sputtering of a TiN or TiON layer on the FeRAM device using a PZT deposited via sol-gel, with functions of a barrier-layer against hydrogen and humidity.
U.S. Pat. No. 5,481,490 discloses the deposition of a thin layer of nitride of aluminum, silicon or titanium on the ferroelectric capacitor, in order to prevent the degradation of the ferroelectric film of the capacitor during the annealing treatments which are foreseen in the manufacturing process of the device, during which the gases H2 and N2 are used.
U.S. Pat. No. 5,591,663 discloses a particular sequence of a manufacturing process of an FeRAM device using conventional materials, which avoids the hydrogen degradation during the annealing treatment.
European published patent application EP-A-0 837 505 discloses a structure comprising a ferroelectric capacitor, wherein a second layer of ferroelectric material PZT is deposited on the already defined structure of the ferroelectric capacitor, so that the second layer of PZT acts as a sacrificial layer, thus preventing hydrogen from reaching and degrading the PZT layer of the capacitor.
European published patent application EP-A-0 911 871 discloses the formation of a thin layer of tantalum and silicon nitride on the ferroelectric capacitor structure, with the function of a barrier layer against the possible diffusion of hydrogen against the ferroelectric layer of the capacitor.
U.S. Pat. No. 5,760,433 discloses the use of a sacrificial layer of a material chemically reactive towards hydrogen which is arranged on the capacitor structure as a protection of the ferroelectric layer of the capacitor. The sacrificial material can contain Sr, Nb, Ta and/or Bi, bismuth oxide, palladium oxide.
U.S. Pat. No. 5,716,875 discloses an FeRAM structure wherein, after annealing in N2+H2, a layer of silicon nitride Si3N4 is deposited on the integrated structure of the transistor and on the back of the substrate wafer for encapsulating (isolating) the structure and preventing in the future the possible effects due to hydrogen retention after the annealing treatment. On a structure so xe2x80x9cisolatedxe2x80x9d with regards to the diffusion of the hydrogen therein sorbed, there is formed the ferroelectric capacitor, which can be therefore advantageously annealed in an oxygen atmosphere without causing degradation of the transistor features. On the other hand, the hydrogen possibly trapped in the so xe2x80x9cinsulatedxe2x80x9d wafer structure will not be able to reach and to degrade the ferroelectric film of the capacitor, thanks to the barrier offered by the nitride layer.
European published patent application EP-A-0 951 059 discloses a particular manufacturing process wherein a final annealing in oxygen would solve the hydrogen degradation which could have taken place during the metallization processes.
U.S. Pat. No. 5,990,513 describes the formation of an inter-level dielectric layer with hydrophilic properties covered by a dielectric layer having reduced hydrophilic properties for protecting the ferroelectric layer during the annealing treatment in hydrogen atmosphere in the case of a ceramic encapsulated device. Ceramic encapsulation requires generally an annealing process at 440 xe2x96xa1.
Japanese published patent application JP-11-293089 describes the formulation of an epoxy resin usable for encapsulating an FeRAM device having features of low hydrogen release at 175 xe2x96xa1 for 90 minutes.
Japanese published patent application JP-11-087633 discloses the use in an FeRAM device of a metal layer formed of a material capable of storing hydrogen during the manufacturing steps. Then, the sorbed hydrogen is expelled by means of thermal treatment under vacuum. The used material can be Pd, V, Ni, Nb, Ti, Fe, Mg, TiFeLaNi2, Ti2Mn3 VNb, TiCo, ZrMn2, Mg2Cu, Mg2Ni, LaCo3, Ti2V8, Ti2C, Ti2Fe, Ti2CoMn.
Japanese published patent application JP-1140761 discloses the use of a layer of Ta or V or Nb deposited on the ferroelectric capacitor for protecting the latter from hydrogen degradation.
Japanese published patent application JP-118355 discloses the use of a hydrogen barrier layer formed of titanium dioxide or silicon nitride arranged under the lower electrode of the ferroelectric capacitor and of a barrier layer arranged over the upper electrode of the ferroelectric capacitor of the same materials or alternatively of titanium nitride or of TiOSi.
Japanese published patent application JP-2000-40799 discloses that, by making a reactive layer of Pbxe2x80x94Ptxe2x80x94Tixe2x80x94O between the PZT ferroelectric layer and the Pt upper electrode of a ferroelectric capacitor, it is possible to prevent the diffusion of hydrogen towards the dielectric and often ferroelectric film of the capacitor.
Until today, the most commonly followed approach is interposing a barrier layer against the diffusion of hydrogen as a protection of the preformed structure of the thin-film capacitor. Obviously, the barrier layer is effective only against the hydrogen coming xe2x80x9cfrom abovexe2x80x9d, that is, the hydrogen which is present in the back-end steps of the manufacturing process of the integrated device. However, the barrier layer is not effective against a possible diffusion of hydrogen xe2x80x9cfrom belowxe2x80x9d, that is, from the hydrogen which has been trapped in the wafer during the annealing treatment and hydrogen of the active structures, which have been formed before making the capacitor. Some known solutions entail the formation of a barrier layer against the diffusion of hydrogen even under the lower electrode of the thin-layer capacitor.
In most of the suggested solutions the approach is anyway protecting the thin layer of dielectric and/or ferroelectric material of the capacitor by means of barrier layers which insulate it against a possible hydrogen diffusion.
The barrier layers tend to stop hydrogen diffusion toward the electrodes and therefore toward the dielectric and/or ferroelectric or having a high dielectric constant material in a passive way. In the case for example of oxides, in addition to the passive effect there is also the chemical reaction between hydrogen and oxide which produces water. This reaction eliminates hydrogen, producing the hydrogen compound.
Also, the materials disclosed in the further Japanese published patent application JP-11-087633 for retaining hydrogen, which is then removed by thermally treating the device under vacuum before the final encapsulation thereof, are capable of sorbing hydrogen in a significant way only at atmospheric pressure.
The main object of the present invention is to provide a thin-film capacitor structure, wherein the dielectric is formed of a material having a high dielectric constant and optionally having also ferroelectric features, protected from the risk of degradation of the dielectric material due to hydrogen diffusion in a more effective way than it is obtainable with the known techniques and without the above mentioned drawbacks and limitations.
This important result is obtained by providing, under the lower electrode and over the upper electrode of the thin-film capacitor, a layer of getter material which is capable of sorbing and retaining hydrogen even at sub-atmospheric pressures without giving rise to chemical bonds (reacting) with hydrogen and/or to morphological modifications of the material.
The sorbing action exerted toward hydrogen by the getter material, in addition to sequestering the hydrogen remaining in the finished device, retains it, thus avoiding degradation of the dielectric-ferroelectric film, without giving rise to generation of water and without chemically reacting with hydrogen.
However, in order to obtain this result, it is necessary that the getter material have hydrogen equilibrium pressures less than 1 mbar at room temperature and that the thickness sufficient for retaining the hydrogen present is compatible with the stringent requirements of compactness of the integrated structures.
Basically, the getter material is an alloy made of zirconium, vanadium and iron, optionally containing minor quantities selected from manganese and the group of rare earth elements, or an alloy of zirconium and at least one of the metals of the group consisting of iron, cobalt, nickel, and optionally containing up to about 15% by weight of rare earth elements.
One layer of getter material is deposited over the layer of material forming the upper electrode of the capacitor and, more preferably, also under the layer forming the lower electrode of the thin-film capacitor, optionally deposited on a first layer of adhesion, for example titanium, interposed between the laminated structure of the capacitor and the support layer.
The getter layer provided under the lower electrode of the thin-film capacitor intercepts the hydrogen which may diffuse from the substrate, if it has been sorbed by the substrate during a previous step of annealing of the wafer in hydrogen. Typically, the lower getter layer can have a lesser thickness (of the order of about 50-100 nm) than the upper getter layer, which can have a thickness also up to about 200 nm.
The lower getter layer can effectively also contribute to sensibly increase the adhesion between an electrode layer, for example of a noble metal or alloy of a noble metal, and the underlying support layer, often in an FeRAM or DRAM device, an amorphous layer of silicon oxide doped with boron and phosphorous (BPSG). In many cases, it can provide the necessary adhesion, thus avoiding the need to interpose a specific adhesion layer with the support layer.
The getter layer which is provided over the upper electrode of the ferroelectric capacitor intercepts and traps the hydrogen which can diffuse through the insulating, metallizing and passivating layers, commonly placed over the defined structure of the ferroelectric thin-film capacitor during the subsequent steps of the fabrication process of the integrated device, in some cases also including the encapsulating steps of the device (packaging).
Both the getter layer formed over the upper electrode of the capacitor and the getter layer optionally formed under (deposited before) the lower electrode of the capacitor can be defined through appropriate masking and attacking steps together with other layers of the structure. In particular, the upper getter layer can result in being self-aligned to the perimeter of definition of the capacitor. Alternatively, the getter layer can be defined through a suitable masking step, also with a wider perimeter than the perimeter of the capacitive coupling area.